Electrical contacts formed on wide band gap semiconductor materials that exhibit ohmic behavior and low barrier resistance are typically formed by depositing metallic layers and applying a subsequent high temperature (>800° C.) anneal/diffusion process in a furnace over a period of minutes or longer. The impact of having a high temperature process step that heats all features on the wafer means that ohmic contacts must be made before any temperature sensitive functional surface features are formed, which greatly restricts the order of processes and the design freedom to form devices out of wide band gap semiconductors. The typical metal silicide procedure using a solid-state diffusion furnace has kept silicon carbide devices from mainstream wafer fabrication lines for decades. It is highly desirable to find a process that only heats the area intended for ohmic contact, while not affecting the other temperature sensitive features
For wide band gap semiconductor materials, such as silicon carbide and gallium nitride, a metal with a sufficiently low work function does not generally exist to create a low enough barrier to exhibit efficient thermionic-emission contacts. Therefore, field emission tunneling ohmic contacts are sought where the band structure of the silicon carbide very near the surface is altered in such a way that electrons can tunnel through a thin electrical barrier instead of jumping over the barrier as with thermionic-emission contacts. In the traditional case of forming a metal silicide in a solid-state diffusion furnace, silicon atoms diffuse and alloy with the metal atoms. The out-diffused silicon alters the band structure of the silicon carbide material to create an ohmic contact with reported resistivity values of 1×10−5 Ohm-cm2.
Another method of forming a tunneling ohmic contact to silicon carbide is by highly doping the semiconductor region near the surface, which produces the desirable change in the band gap for tunneling contacts. Substrate doping is typically limited by the boule growth process to ˜5×1018 cm−3 for wide band gap conductive substrates. Thus, achieving a high level of doping, (e.g., >>5×1018 cm−3), is typically done by ion implantation or by epitaxial growth, both of which require high temperature (>800° C.) furnaces and greatly restrict the order of processes and design freedom to form devices out of wide band gap semiconductors. In addition, both ion implantation and epitaxial growth limit the ability to incorporate dopants to about 2 orders of magnitude below the solubility limit. Finally, the formation of the ohmic contact is completed after the subsequent deposition of metals on the highly doped semiconductor surface.
Another method of forming a tunneling ohmic contact to silicon carbide is by highly doping the semiconductor region near the surface through laser doping. Laser doping is a process where the ambient above the semiconductor surface is controlled in a sealed ampoule and a highly concentrated dopant gas is introduced into the ampoule. A laser pulse is incident through a window in the ampoule and melts the surface of the semiconductor at which time the highly concentrated dopant gas diffuses into the melted surface of the semiconductor and activates upon solidification. Dopant levels near the solubility limit have been reached using laser doping. Ohmic contact resistivities on the order of 1×10−5 Ohm-cm2 have been reported for silicon carbide once metals are deposited post laser treatment.
It is highly desirable to thin a semiconductor wafer by standard grinding and polishing processes to reduce the electrical resistance created by the substrate that is limited in electrical conductivity due to the limited doping levels available in boule growth processes. However, the ability to accurately form topside features through photolithographic processes, material depositioned, and etching is greatly inhibited when the wafer is thinned to the point of excessive fragility and warpage. Attaching thinned semiconductor wafers to wafer carriers is a typical approach to counteract excessive warpage and allow critical topside processes to be accurately completed, but this approach requires additional process steps and challenges. Therefore, it is desired to perform the wafer thinning process after or nearly after all topside features are completed so that the use of a wafer carrier is not required. Furthermore, it is desired that after wafer thinning there are no high temperature processes utilized that compromise the thinned wafer's structural integrity or the functional features already formed. In addition, it is desired that high volume semiconductor production have an ohmic contact process that does not require the use of sealed, pressurized ampoules.